HW Implementation and Verification for Crypto Engine Accelerator
- Surveyed 500+ papers and co-developed 4 novel, area-efficient lightweight AES state-array architectures, personally architecting one variant.
- Collaboratively implemented and verified the RTL core in SystemVerilog using a UVM testbench with directed and constrained-random testing for functional coverage closure.
- Integrated the accelerator onto an ARM Cortex-M0 AHB bus, successfully bringing up the full SoC and debugging hardware-software execution with bare-metal C drivers.





